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• Cortex-A7 instruction cycle timings

  15 mai 2014, par Mans — ARM

  The Cortex-A7 ARM core is a popular choice in low-power and low-cost designs. Unfortunately, the public TRM does not include instruction timing information. It does reveal that execution is in-order which makes measuring the throughput and latency for individual instructions relatively straight-forward.

  The table below lists the measured issue cycles (inverse throughput) and result latency of some commonly used instructions.

  It should be noted that in some cases, the perceived latency depends on the instruction consuming the result. Most of the values were measured with the result used as input to the same instruction. For instructions with multiple outputs, the latencies of the result registers may also differ.

  Finally, although instruction issue is in-order, completion is out of order, allowing independent instructions to issue and complete unimpeded while a multi-cycle instruction is executing in another unit. For example, a 3-cycle MUL instruction does not block ADD instructions following it in program order.

  ALU instructions	Issue cycles	Result latency
  MOV Rd, Rm	1/2	1
  ADD Rd, Rn, #imm	1/2	1
  ADD Rd, Rn, Rm	1	1
  ADD Rd, Rn, Rm, LSL #imm	1	1
  ADD Rd, Rn, Rm, LSL Rs	1	1
  LSL Rd, Rn, #imm	1	2
  LSL Rd, Rn, Rs	1	2
  QADD Rd, Rn, Rm	1	2
  QADD8 Rd, Rn, Rm	1	2
  QADD16 Rd, Rn, Rm	1	2
  CLZ Rd, Rm	1	1
  RBIT Rd, Rm	1	2
  REV Rd, Rm	1	2
  SBFX Rd, Rn	1	2
  BFC Rd, #lsb, #width	1	2
  BFI Rd, Rn, #lsb, #width	1	2
  NOTE : Shifted operands and shift amounts needed one cycle early.
  Multiply instructions	Issue cycles	Result latency
  MUL Rd, Rn, Rm	1	3
  MLA Rd, Rn, Rm, Ra	1	31
  SMULL Rd, RdHi, Rn, Rm	1	3
  SMLAL Rd, RdHi, Rn, Rm	1	31
  SMMUL Rd, Rn, Rm	1	3
  SMMLA Rd, Rn, Rm, Ra	1	31
  SMULBB Rd, Rn, Rm	1	3
  SMLABB Rd, Rn, Rm, Ra	1	31
  SMULWB Rd, Rn, Rm	1	3
  SMLAWB Rd, Rn, Rm, Ra	1	31
  SMUAD Rd, Rn, Rm	1	3
  1 Accumulator forwarding allows back to back MLA instructions without delay.
  Divide instructions	Issue cycles	Result latency
  SDIV Rd, Rn, Rm	4-20	6-22
  UDIV Rd, Rn, Rm	3-19	5-21
  Load/store instructions	Issue cycles	Result latency
  LDR Rt, [Rn]	1	3
  LDR Rt, [Rn, #imm]	1	3
  LDR Rt, [Rn, Rm]	1	3
  LDR Rt, [Rn, Rm, lsl #imm]	1	3
  LDRD Rt, Rt2, [Rn]	1	3-4
  LDM Rn, regs	1-8	3-10
  STR Rt, [Rn]	1	2
  STRD Rt, Rt2, [Rn]	1	2
  STM Rn, regs	1-10	2-12
  NOTE : Load results are forwarded to dependent stores without delay.
  VFP instructions	Issue cycles	Result latency
  VMOV.F32 Sd, Sm	1	4
  VMOV.F64 Dd, Dm	1	4
  VNEG.F32 Sd, Sm	1	4
  VNEG.F64 Dd, Dm	1	4
  VABS.F32 Sd, Sm	1	4
  VABS.F64 Dd, Dm	1	4
  VADD.F32 Sd, Sn, Sm	1	4
  VADD.F64 Dd, Dn, Dm	1	4
  VMUL.F32 Sd, Sn, Sm	1	4
  VMUL.F64 Dd, Dn, Dm	4	7
  VMLA.F32 Sd, Sn, Sm	1	81
  VMLA.F64 Dd, Dn, Dm	4	112
  VFMA.F32 Sd, Sn, Sm	1	81
  VFMA.F64 Dd, Dn, Dm	5	82
  VDIV.F32 Sd, Sn, Sm	15	18
  VDIV.F64 Dd, Dn, Dm	29	32
  VSQRT.F32 Sd, Sm	14	17
  VSQRT.F64 Dd, Dm	28	31
  VCVT.F32.F64 Sd, Dm	1	4
  VCVT.F64.F32 Dd, Sm	1	4
  VCVT.F32.S32 Sd, Sm	1	4
  VCVT.F64.S32 Dd, Sm	1	4
  VCVT.S32.F32 Sd, Sm	1	4
  VCVT.S32.F64 Sd, Dm	1	4
  VCVT.F32.S32 Sd, Sd, #fbits	1	4
  VCVT.F64.S32 Dd, Dd, #fbits	1	4
  VCVT.S32.F32 Sd, Sd, #fbits	1	4
  VCVT.S32.F64 Dd, Dd, #fbits	1	4
  1 5 cycles with dependency only on accumulator. 2 8 cycles with dependency only on accumulator.
  NEON integer instructions	Issue cycles	Result latency
  VADD.I8 Dd, Dn, Dm	1	4
  VADDL.S8 Qd, Dn, Dm	2	4
  VADD.I8 Qd, Qn, Qm	2	4
  VMUL.I8 Dd, Dn, Dm	2	4
  VMULL.S8 Qd, Dn, Dm	2	4
  VMUL.I8 Qd, Qn, Qm	4	4
  VMLA.I8 Dd, Dn, Dm	2	4
  VMLAL.S8 Qd, Dn, Dm	2	4
  VMLA.I8 Qd, Qn, Qm	4	4
  VADD.I16 Dd, Dn, Dm	1	4
  VADDL.S16 Qd, Dn, Dm	2	4
  VADD.I16 Qd, Qn, Qm	2	4
  VMUL.I16 Dd, Dn, Dm	1	4
  VMULL.S16 Qd, Dn, Dm	2	4
  VMUL.I16 Qd, Qn, Qm	2	4
  VMLA.I16 Dd, Dn, Dm	1	4
  VMLAL.S16 Qd, Dn, Dm	2	4
  VMLA.I16 Qd, Qn, Qm	2	4
  VADD.I32 Dd, Dn, Dm	1	4
  VADDL.S32 Qd, Dn, Dm	2	4
  VADD.I32 Qd, Qn, Qm	2	4
  VMUL.I32 Dd, Dn, Dm	2	4
  VMULL.S32 Qd, Dn, Dm	2	4
  VMUL.I32 Qd, Qn, Qm	4	4
  VMLA.I32 Dd, Dn, Dm	2	4
  VMLAL.S32 Qd, Dn, Dm	2	4
  VMLA.I32 Qd, Qn, Qm	4	4
  NEON floating-point instructions	Issue cycles	Result latency
  VADD.F32 Dd, Dn, Dm	2	4
  VADD.F32 Qd, Qn, Qm	4	4
  VMUL.F32 Dd, Dn, Dm	2	4
  VMUL.F32 Qd, Qn, Qm	4	4
  VMLA.F32 Dd, Dn, Dm	2	81
  VMLA.F32 Qd, Qn, Qm	4	81
  1 5 cycles with dependency only on accumulator.
  NEON permute instructions	Issue cycles	Result latency
  VEXT.n Dd, Dn, Dm, #imm	1	4
  VEXT.n Qd, Qn, Qm, #imm	2	5
  VTRN.n Dd, Dn, Dm	2	5
  VTRN.n Qd, Qn, Qm	4	5
  VUZP.n Dd, Dn, Dm	2	5
  VUZP.n Qd, Qn, Qm	4	6
  VZIP.n Dd, Dn, Dm	2	5
  VZIP.n Qd, Qn, Qm	4	6
  VTBL.8 Dd, Dn, Dm	1	4
  VTBL.8 Dd, Dn-Dn+1, Dm	1	4
  VTBL.8 Dd, Dn-Dn+2, Dm	2	5
  VTBL.8 Dd, Dn-Dn+3, Dm	2	5

• X264 Encoder API

  16 avril 2014, par user1884325

  I’m studying the X264 API for encoding images.

  So far I’ve built the X264 library and the following code snippet shows how far I am :

    int frame_size;
  
    x264_t* encoder;
  
    x264_picture_t pic_in, pic_out;
  
    x264_param_t x264Param;
  
    int fps = 20;
  
    int width = 1280;
  
    int height = 720;
  
    x264_nal_t* nals;
  
    int i_nals;
  
  
  
    x264_param_default_preset(&x264Param, "veryfast", "zerolatency");
  
    x264Param.i_threads = 1;
  
    x264Param.i_width = 1280;
  
    x264Param.i_height = 720;
  
    x264Param.i_fps_num = fps;
  
    x264Param.i_fps_den = 1;
  
    x264Param.i_keyint_max = fps;
  
    x264Param.b_intra_refresh = 1;
  
    x264Param.rc.i_rc_method = X264_RC_CRF;
  
    x264Param.rc.f_rf_constant = 25;
  
    x264Param.rc.f_rf_constant_max = 35;
  
    x264Param.b_repeat_headers = 1;
  
    x264Param.b_annexb = 1;
  
    x264_param_apply_profile(&x264Param, "baseline");
  
  
  
    encoder = x264_encoder_open(&x264Param);
  
  
  
    x264_picture_alloc(&pic_in, X264_CSP_BGR, width, height);
  
  
  
    /* How to fill in bitmap data? */
  
  
  
    frame_size = x264_encoder_encode(encoder, &nals, &i_nals, &pic_in, &pic_out);
  
    if (frame_size >= 0)
  
    {
  
        printf("OK\n");
  
    }

  So I’m trying to encode a 24bit BGR bitmap image. However, the x264 header file doesn’t show any API function for writing the bitmap image to the encoder. How is this done ?

  EDIT

  This code snippet seems to work. I would appreciate a review and some comments. Thanks.

    int frame_size;
  
    int accum_frame_size;
  
    x264_t* encoder;
  
    x264_picture_t pic_in, pic_out;
  
    x264_param_t x264Param;
  
    int fps = 20;
  
    int width = 1280;
  
    int height = 720;
  
    x264_nal_t* nals;
  
    int i_nals;
  
    int64_t frameCount = 0;
  
    int k;
  
  
  
    for (k = 0; k < (1280*3*720); k++)
  
    {
  
       bgr[k] = rand();
  
    }
  
  
  
    x264_param_default_preset(&x264Param, "veryfast", "zerolatency");
  
    x264Param.i_threads = 1;
  
    x264Param.i_width = 1280;
  
    x264Param.i_height = 720;
  
    x264Param.i_fps_num = fps;
  
    x264Param.i_fps_den = 1;
  
    x264Param.i_keyint_max = fps;
  
    x264Param.b_intra_refresh = 1;
  
    x264Param.rc.i_rc_method = X264_RC_CRF;
  
    x264Param.i_csp = X264_CSP_BGR;
  
    x264Param.rc.f_rf_constant = 25;
  
    x264Param.rc.f_rf_constant_max = 35;
  
    x264Param.b_repeat_headers = 1;
  
    x264Param.b_annexb = 1;
  
    x264_param_apply_profile(&x264Param, "baseline");
  
  
  
    encoder = x264_encoder_open(&x264Param);
  
  
  
    x264_picture_alloc(&pic_in, X264_CSP_BGR, width, height);
  
  
  
    /* Load 24-bit BGR bitmap */
  
    pic_in.img.i_csp = X264_CSP_BGR;
  
    pic_in.img.i_plane = 1;
  
    pic_in.img.i_stride[0] = 3 * 1280;
  
    pic_in.img.plane[0] = bgr;
  
    pic_in.i_pts = frameCount;
  
    pic_in.i_type = X264_TYPE_AUTO;
  
    pic_out.i_pts = frameCount;
  
  
  
    /* Returns a frame size of 912 for first frame in this case */
  
    frame_size = x264_encoder_encode(encoder, &nals, &i_nals, &pic_in, &pic_out);
  
  
  
    printf("Decoder returned frame size = %d \n", frame_size);
  
    printf("Decoder returned %d NAL units \n", i_nals);
  
    if (frame_size >= 0)
  
    {
  
       int i;
  
       int j;
  
  
  
  
  
       accum_frame_size = 0;
  
       for (i = 0; i < i_nals; i++)
  
       {
  
          printf("******************* NAL %d (%d bytes) *******************\n", i, nals[i].i_payload);
  
          for (j = 0; j < nals[i].i_payload; j++)
  
          {
  
             if (j == 0) printf("First 10 bytes: ");
  
             if (j < 10) printf("%02X |", nals[i].p_payload[j]);
  
             accum_frame_size++;
  
          }
  
          printf("\n");
  
  
  
       }
  
    }
  
  
  
    printf("Verified frame size = %d \n", accum_frame_size);

  EDIT #2
  The encoder outputs this :

       x264 [error]: baseline profile doesn't support 4:4:4
  
       x264 [info]: using cpu capabilities: MMX2 SSE2Fast SSSE3 SSE4.2 AVX
  
       x264 [info]: profile High 4:4:4 Predictive, level 3.1, 4:4:4 8-bit
  
       Decoder returned frame size = 1467194
  
       Decoder returned 4 NAL units
  
       ******************* NAL 0 (31 bytes) *******************
  
       First 10 bytes: 00 |00 |00 |01 |67 |F4 |00 |1F |91 |89 |
  
       ******************* NAL 1 (8 bytes) *******************
  
       First 10 bytes: 00 |00 |00 |01 |68 |EF |1F |2C |
  
       ******************* NAL 2 (595 bytes) *******************
  
       First 10 bytes: 00 |00 |01 |06 |05 |FF |FF |4C |DC |45 |
  
       ******************* NAL 3 (1466560 bytes) *******************
  
       First 10 bytes: 00 |00 |01 |65 |88 |82 |0A |FF |F5 |B0 |
  
       Verified frame size = 1467194

  Isn’t each NAL unit supposed to start with 0x00 0x00 0x00 0x01 ?

  szatmary : I appreciate your valuable feedback. So you’re saying that each NAL unit does not necessarily start with 0,0,0,1. However, I’m a bit unclear on your answer. Are you implying that with a certain configuration the NAL units will start with 0,0,0,1 ? If so, which configuration is that ? I need to make sure that each NAL unit I transmit out on the network to a remote receiver starts with 0,0,0,1. Prior to exploring the x264 library I was using the x264 exe and piped BMP data in and encoded data out from the x264 process. I then parsed the encoder output and looked for NAL units by looking for 0,0,0,1. How do I accomplish the same with the x264 library ?

  Regarding libswscale :

  I downloaded the ffmpeg source and ran configure and make in MINGW. After the process had completed I couldn’t find anything but a number of .exe files. How do I build actual static libraries (.lib) which I can use in a Visual Studio project ?

• Revision 48b0891370 : Inverse 16x16 2D-DCT SSSE3 implementation This commit enables the SSSE3 impleme

  22 mai 2014, par Jingning Han

  Changed Paths :
   Modify /vp9/common/vp9_rtcd_defs.pl

  
   Modify /vp9/common/x86/vp9_idct_intrin_sse2.c

  
   Add /vp9/common/x86/vp9_idct_intrin_sse2.h

  
   Add /vp9/common/x86/vp9_idct_intrin_ssse3.c

  
   Modify /vp9/vp9_common.mk

  
  
  Inverse 16x16 2D-DCT SSSE3 implementation

  This commit enables the SSSE3 implementation of full inverse 16x16
  2D-DCT. The unit runtime goes down from 1642 cycles to 1519 cycles,
  about 7% speed-up.

  Change-Id : I14d2fdf9da1fb4ed1e5db7ce24f77a1bfc8ea90d