Recherche avancée

Sur d’autres sites (7931)

• FFMPEG tee muxer giving "Output file #0 does not contain any stream"

  31 août 2020, par Giorgi Aptsiauri

  I am trying to create two streams : one is mpegts UDP stream another - rtmp to Twitch servers.

  


  This command works :

  


    ffmpeg -threads:v 2 -threads:a 16 -filter_threads 2 -thread_queue_size 16 -y \
 -f dshow -video_size 1920x1080 -pixel_format uyvy422 -framerate 25 -rtbufsize 500M -i video="Decklink Video Capture" \
 -f dshow -rtbufsize 100M -i audio="Decklink Audio Capture" \
 -preset ultrafast -c:v libx264 -tune zerolatency -b:v 900k -map 0:v:0 -f mpegts udp://127.0.0.1:5555 \ 
 -pix_fmt yuv420p -c:v libx264 -crf 20 -tune zerolatency -f flv rtmp://live-fra05.twitch.tv/app/stream_key


  


  But it requires double the encoding CPU power.

  


  So, following this, I rewrote the command like this :

  


  ffmpeg -threads:v 2 -threads:a 16 -filter_threads 2 -thread_queue_size 16 -y \
 -f dshow -video_size 1920x1080 -pixel_format uyvy422 -framerate 25 -rtbufsize 500M -i video="Decklink Video Capture" \
 -f dshow -rtbufsize 100M -i audio="Decklink Audio Capture" \
 -preset ultrafast -c:v libx264 -tune zerolatency -b:v 900k \
 -f tee "[select=\'0:v:0\':f=mpegts]udp://127.0.0.1:5555|[select=\'0:v:0,1:a:0\':f=flv]rtmp://live-fra05.twitch.tv/app/stream_key"


  


  By writing -f tee "[select=\'0:v:0\':f=mpegts]udp://127.0.0.1:5555|[select=\'0:v:0,1:a:0\':f=flv]rtmp://live-fra05.twitch.tv/app/stream_key", I mean :

  


  

  • create UDP stream at udp ://127.0.0.1:5555 and only include video stream from "Decklink Video Capture"

  


  • create RTMP stream where we include the same video stream as above and also the audio stream from "Decklink Audio Capture"

  


  


  I get the error message :

  


  Output file #0 does not contain any stream


  


  How do I fix this ? I assume I made a mistake in the command.

  


• Video from images to mp4 in nvidia GPU

  16 août 2019, par M.y

  I am trying to encode a h264 .mp4 video created from .jpg images using a 1070ti nvidia cuda power, having a a crossfade transition between each image.
  I am able to render the video in GPU using the flags -c:v h264_nvenc, I see a short peak in the GPU encoding, but with a long period of computer CPU hight load, I guess preparing the transitioning images. But the image preparation it happens on cpu/ram due the -filter_complex and is quite slow.
  This works :

  ffmpeg.exe, -y, -loop, 1, -t, 2.5, -i, 1565957420594_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565957453659_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565957487743_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565957525280_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565957587308_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565957644898_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565957859119_labeled.jpg, -loop, 1, -t, 2.5, -i,1565959133561_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565959412948_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565959501884_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565959755432_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565959882380_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565960023185_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565960157174_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565960683303_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565961151548_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565961230278_labeled.jpg, -loop, 1, -t, 2.5, -i, 1565961671766_labeled.jpg, -loop, 1, -t, 2.5, -i, final.jpg, -loop, 1, -t, 2.5, -i, final.jpg, -c:v, h264_nvenc, -preset, fast, -filter_complex, [1]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+0.5/TB[f0];[2]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+1.0/TB[f1];[3]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+1.5/TB[f2];[4]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+2.0/TB[f3];[5]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+2.5/TB[f4];[6]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+3.0/TB[f5];[7]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+3.5/TB[f6];[8]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+4.0/TB[f7];[9]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+4.5/TB[f8];[10]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+5.0/TB[f9];[11]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+5.5/TB[f10];[12]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+6.0/TB[f11];[13]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+6.5/TB[f12];[14]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+7.0/TB[f13];[15]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+7.5/TB[f14];[16]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+8.0/TB[f15];[17]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+8.5/TB[f16];[18]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+9.0/TB[f17];[19]fade=d=0.5:t=in:alpha=1,setpts=PTS-STARTPTS+9.5/TB[f18];[0][f0]overlay[bg1];[bg1][f1]overlay[bg2];[bg2][f2]overlay[bg3];[bg3][f3]overlay[bg4];[bg4][f4]overlay[bg5];[bg5][f5]overlay[bg6];[bg6][f6]overlay[bg7];[bg7][f7]overlay[bg8];[bg8][f8]overlay[bg9];[bg9][f9]overlay[bg10];[bg10][f10]overlay[bg11];[bg11][f11]overlay[bg12];[bg12][f12]overlay[bg13];[bg13][f13]overlay[bg14];[bg14][f14]overlay[bg15];[bg15][f15]overlay[bg16];[bg16][f16]overlay[bg17];[bg17][f17]overlay[bg18];[bg18][f18]overlay[v], -map, [v], -movflags, +faststart, output.mp4

  I am trying to do all work in the GPU, theoretically I can encode all images in GPU memory using in each -i the flags "-hwaccel cuvid -c:v mjpeg_cuvid" I receive the following error :

  [mjpeg_cuvid @ 00000000024ef980] ignoring invalid SAR: 0/0
  
  Impossible to convert between the formats supported by the filter 'graph 0 input from stream 1:0' and the filter 'auto_scaler_0'
  
  Error reinitializing filters!
  
  Failed to inject frame into filter network: Function not implemented
  
  Error while processing the decoded data for stream #0:0

  Is there a way to load images in the GPU with the "fade" flag applied ?

  Thanks in advance !

• ARM inline asm secrets

  6 juillet 2010, par Mans — ARM, Compilers

  Although I generally recommend against using GCC inline assembly, preferring instead pure assembly code in separate files, there are occasions where inline is the appropriate solution. Should one, at a time like this, turn to the GCC documentation for guidance, one must be prepared for a degree of disappointment. As it happens, much of the inline asm syntax is left entirely undocumented. This article attempts to fill in some of the blanks for the ARM target.
  

  Constraints

  Each operand of an inline asm block is described by a constraint string encoding the valid representations of the operand in the generated assembly. For example the “r” code denotes a general-purpose register. In addition to the standard constraints, ARM allows a number of special codes, only some of which are documented. The full list, including a brief description, is available in the constraints.md file in the GCC source tree. The following table is an extract from this file consisting of the codes which are meaningful in an inline asm block (a few are only useful in the machine description itself).

  f	Legacy FPA registers f0-f7.
  t	The VFP registers s0-s31.
  v	The Cirrus Maverick co-processor registers.
  w	The VFP registers d0-d15, or d0-d31 for VFPv3.
  x	The VFP registers d0-d7.
  y	The Intel iWMMX co-processor registers.
  z	The Intel iWMMX GR registers.
  l	In Thumb state the core registers r0-r7.
  h	In Thumb state the core registers r8-r15.
  j	A constant suitable for a MOVW instruction. (ARM/Thumb-2)
  b	Thumb only. The union of the low registers and the stack register.
  I	In ARM/Thumb-2 state a constant that can be used as an immediate value in a Data Processing instruction. In Thumb-1 state a constant in the range 0 to 255.
  J	In ARM/Thumb-2 state a constant in the range -4095 to 4095. In Thumb-1 state a constant in the range -255 to -1.
  K	In ARM/Thumb-2 state a constant that satisfies the I constraint if inverted. In Thumb-1 state a constant that satisfies the I constraint multiplied by any power of 2.
  L	In ARM/Thumb-2 state a constant that satisfies the I constraint if negated. In Thumb-1 state a constant in the range -7 to 7.
  M	In Thumb-1 state a constant that is a multiple of 4 in the range 0 to 1020.
  N	Thumb-1 state a constant in the range 0 to 31.
  O	In Thumb-1 state a constant that is a multiple of 4 in the range -508 to 508.
  Pa	In Thumb-1 state a constant in the range -510 to +510
  Pb	In Thumb-1 state a constant in the range -262 to +262
  Ps	In Thumb-2 state a constant in the range -255 to +255
  Pt	In Thumb-2 state a constant in the range -7 to +7
  G	In ARM/Thumb-2 state a valid FPA immediate constant.
  H	In ARM/Thumb-2 state a valid FPA immediate constant when negated.
  Da	In ARM/Thumb-2 state a const_int, const_double or const_vector that can be generated with two Data Processing insns.
  Db	In ARM/Thumb-2 state a const_int, const_double or const_vector that can be generated with three Data Processing insns.
  Dc	In ARM/Thumb-2 state a const_int, const_double or const_vector that can be generated with four Data Processing insns. This pattern is disabled if optimizing for space or when we have load-delay slots to fill.
  Dn	In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov immediate instruction.
  Dl	In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or vbic instruction.
  DL	In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or vand instruction.
  Dv	In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts instruction.
  Dy	In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd instruction.
  Ut	In ARM/Thumb-2 state an address valid for loading/storing opaque structure types wider than TImode.
  Uv	In ARM/Thumb-2 state a valid VFP load/store address.
  Uy	In ARM/Thumb-2 state a valid iWMMX load/store address.
  Un	In ARM/Thumb-2 state a valid address for Neon doubleword vector load/store instructions.
  Um	In ARM/Thumb-2 state a valid address for Neon element and structure load/store instructions.
  Us	In ARM/Thumb-2 state a valid address for non-offset loads/stores of quad-word values in four ARM registers.
  Uq	In ARM state an address valid in ldrsb instructions.
  Q	In ARM/Thumb-2 state an address that is a single base register.

  Operand codes

  Within the text of an inline asm block, operands are referenced as %0, %1 etc. Register operands are printed as rN, memory operands as [rN, #offset], and so forth. In some situations, for example with operands occupying multiple registers, more detailed control of the output may be required, and once again, an undocumented feature comes to our rescue.

  Special code letters inserted between the % and the operand number alter the output from the default for each type of operand. The table below lists the more useful ones.

  c	An integer or symbol address without a preceding # sign
  B	Bitwise inverse of integer or symbol without a preceding #
  L	The low 16 bits of an immediate constant
  m	The base register of a memory operand
  M	A register range suitable for LDM/STM
  H	The highest-numbered register of a pair
  Q	The least significant register of a pair
  R	The most significant register of a pair
  P	A double-precision VFP register
  p	The high single-precision register of a VFP double-precision register
  q	A NEON quad register
  e	The low doubleword register of a NEON quad register
  f	The high doubleword register of a NEON quad register
  h	A range of VFP/NEON registers suitable for VLD1/VST1
  A	A memory operand for a VLD1/VST1 instruction
  y	S register as indexed D register, e.g. s5 becomes d2[1]