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Rennes Emotion Map 2010-11
19 octobre 2011, par
Mis à jour : Juillet 2013
Langue : français
Type : Texte
Autres articles (88)
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Personnaliser en ajoutant son logo, sa bannière ou son image de fond
5 septembre 2013, parCertains thèmes prennent en compte trois éléments de personnalisation : l’ajout d’un logo ; l’ajout d’une bannière l’ajout d’une image de fond ;
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MediaSPIP v0.2
21 juin 2013, parMediaSPIP 0.2 est la première version de MediaSPIP stable.
Sa date de sortie officielle est le 21 juin 2013 et est annoncée ici.
Le fichier zip ici présent contient uniquement les sources de MediaSPIP en version standalone.
Comme pour la version précédente, il est nécessaire d’installer manuellement l’ensemble des dépendances logicielles sur le serveur.
Si vous souhaitez utiliser cette archive pour une installation en mode ferme, il vous faudra également procéder à d’autres modifications (...) -
Mise à disposition des fichiers
14 avril 2011, parPar défaut, lors de son initialisation, MediaSPIP ne permet pas aux visiteurs de télécharger les fichiers qu’ils soient originaux ou le résultat de leur transformation ou encodage. Il permet uniquement de les visualiser.
Cependant, il est possible et facile d’autoriser les visiteurs à avoir accès à ces documents et ce sous différentes formes.
Tout cela se passe dans la page de configuration du squelette. Il vous faut aller dans l’espace d’administration du canal, et choisir dans la navigation (...)
Sur d’autres sites (11912)
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Announcement : Piwik to focus on Reliability, Performance and Security
To our valued team and community,
Well, we have moved fast and achieved so much during the past few months. Relentlessly releasing major version after major version… We got a lot done including several major new features !
The speed of adding new features was a great showcase of how agile our small teams and the larger community are. And I’m so proud to see automated testing becoming common practice among everyone hacking on Piwik !
For the next few months until the new year we will focus on making what we have better. We will fix those rare but longstanding critical bugs, and aim to solve all Major issues and other must-have performance and general improvements. The core team and Piwik PRO will have the vision of making the existing Piwik and all plugins very stable and risk free. This includes edge cases, general bugs but also specific performance issues for high traffic or issues with edge case data payloads.
We’ll be more pro-active and take Piwik platform to the next level of Performance, Security, Privacy & Reliability ! We will prove to the world that Free/Libre Web software can be of the highest standard of quality. By focusing on quality we will make Piwik even easier to maintain and improve in the future. We are building the best open platform that will let every user liberate their data and keep full control of it.
If you have any feedback or questions get in touch or let’s continue the discussion in the forum.
Thank you for your trust and for liberating your data with Piwik,
Matthieu Aubry
Piwik founderMore information
- How long is each release of Piwik maintained for ? (FAQ)
- When is the next release of Piwik ? What is the release schedule ? (FAQ)
- Pulse of Piwik : our monthly pulse report shows 27 different people contributed to Piwik core in the last month !
This is an amazing testament of the power of free/libre software and yet we think this is just the beginning. We hope more developers will join and contribute to the Piwik project !
-
Announcement : Piwik to focus on Reliability, Performance and Security
To our valued team and community,
Well, we have moved fast and achieved so much during the past few months. Relentlessly releasing major version after major version… We got a lot done including several major new features !
The speed of adding new features was a great showcase of how agile our small teams and the larger community are. And I’m so proud to see automated testing becoming common practice among everyone hacking on Piwik !
For the next few months until the new year we will focus on making what we have better. We will fix those rare but longstanding critical bugs, and aim to solve all Major issues and other must-have performance and general improvements. The core team and Piwik PRO will have the vision of making the existing Piwik and all plugins very stable and risk free. This includes edge cases, general bugs but also specific performance issues for high traffic or issues with edge case data payloads.
We’ll be more pro-active and take Piwik platform to the next level of Performance, Security, Privacy & Reliability ! We will prove to the world that Free/Libre Web software can be of the highest standard of quality. By focusing on quality we will make Piwik even easier to maintain and improve in the future. We are building the best open platform that will let every user liberate their data and keep full control of it.
If you have any feedback or questions get in touch or let’s continue the discussion in the forum.
Thank you for your trust and for liberating your data with Piwik,
Matthieu Aubry
Piwik founderMore information
- How long is each release of Piwik maintained for ? (FAQ)
- When is the next release of Piwik ? What is the release schedule ? (FAQ)
- Pulse of Piwik : our monthly pulse report shows 27 different people contributed to Piwik core in the last month !
This is an amazing testament of the power of free/libre software and yet we think this is just the beginning. We hope more developers will join and contribute to the Piwik project !
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Bit-field badness
30 janvier 2010, par Mans — Compilers, OptimisationConsider the following C code which is based on an real-world situation.
struct bf1_31 unsigned a:1 ; unsigned b:31 ; ;
void func(struct bf1_31 *p, int n, int a)
int i = 0 ;
do
if (p[i].a)
p[i].b += a ;
while (++i < n) ;
How would we best write this in ARM assembler ? This is how I would do it :
func : ldr r3, [r0], #4 tst r3, #1 add r3, r3, r2, lsl #1 strne r3, [r0, #-4] subs r1, r1, #1 bgt func bx lr
The
add
instruction is unconditional to avoid a dependency on the comparison. Unrolling the loop would mask the latency of theldr
instruction as well, but that is outside the scope of this experiment.Now compile this code with
gcc -march=armv5te -O3
and watch in horror :func : push r4 mov ip, #0 mov r4, r2 loop : ldrb r3, [r0] add ip, ip, #1 tst r3, #1 ldrne r3, [r0] andne r2, r3, #1 addne r3, r4, r3, lsr #1 orrne r2, r2, r3, lsl #1 strne r2, [r0] cmp ip, r1 add r0, r0, #4 blt loop pop r4 bx lr
This is nothing short of awful :
- The same value is loaded from memory twice.
- A complicated mask/shift/or operation is used where a simple shifted add would suffice.
- Write-back addressing is not used.
- The loop control counts up and compares instead of counting down.
- Useless
mov
in the prologue ; swapping the roles orr2
andr4
would avoid this. - Using
lr
in place ofr4
would allow the return to be done withpop {pc}
, saving one instruction (ignoring for the moment that no callee-saved registers are needed at all).
Even for this trivial function the gcc-generated code is more than twice the optimal size and slower by approximately the same factor.
The main issue I wanted to illustrate is the poor handling of bit-fields by gcc. When accessing bitfields from memory, gcc issues a separate load for each field even when they are contained in the same aligned memory word. Although each load after the first will most likely hit L1 cache, this is still bad for several reasons :
- Loads have typically two or three cycles result latency compared to one cycle for data processing instructions. Any bit-field can be extracted from a register with two shifts, and on ARM the second of these can generally be achieved using a shifted second operand to a following instruction. The ARMv6T2 instruction set also adds the
SBFX
andUBFX
instructions for extracting any signed or unsigned bit-field in one cycle. - Most CPUs have more data processing units than load/store units. It is thus more likely for an ALU instruction than a load/store to issue without delay on a superscalar processor.
- Redundant memory accesses can trigger early flushing of store buffers rendering these less efficient.
No gcc bashing is complete without a comparison with another compiler, so without further ado, here is the ARM RVCT output (
armcc --cpu 5te -O3
) :func : mov r3, #0 push r4, lr loop : ldr ip, [r0, r3, lsl #2] tst ip, #1 addne ip, ip, r2, lsl #1 strne ip, [r0, r3, lsl #2] add r3, r3, #1 cmp r3, r1 blt loop pop r4, pc
This is much better, the core loop using only one instruction more than my version. The loop control is counting up, but at least this register is reused as offset for the memory accesses. More remarkable is the push/pop of two registers that are never used. I had not expected to see this from RVCT.
Even the best compilers are still no match for a human.